芯片ESD测试 HBM测试 静电放电抗扰度试验等级 第三方检测机构

aec_中关于hbm测试的特殊要求：

一，测试电压要求，测试过程中不允许跳过电压进行测试

3.1 aec hbm testing shall be done at the followinglevels and skipping voltagelevels is not allowed:

a. 500 v, 1000 v and 2000 v（加电压按照500v一个step进行加）

b. if failures are observed at 500 v, hbm testing at 250 v shall bedone. if failures are observed at 250 v, hbm testing at 125 v shallbe done. if the device fails at 250 v and a tester that meetswaveform re at 125 v is not available, the part shall beclassified class 0a (i.e., < 125 v).

c. voltage levels above 2000v may be done for margin, higherthreshold targets or high robustness characterization.（大于2000v也需要测试一下窗口有多大）

二，pin stress combinations

4.1 devices with six (6) pins or less shall be tested with allpossible pin pair combinations (one pin connected to terminal a,another pin connected to terminal b) regardless of pin name orfunction.

4.2 hbm stress for aec q100 shall be initially doneusing js-001 table 2b, withthe following exceptions:

a. hbmstress using a low parasitic tester (lpt) (see section4.3 below)

b. if a tester artifact is deemed to cause a false hbm failure,options contained within js-001 table 2a may beused. （tester的原因导致的fail，也可以转化为table2a）

c. if a failure is deemed to be caused by cumulative stress,options contained within js-001 table 2a may beused. （如果累积fail出现，可以转化为table2a）

4.3 aec q100 stress using a low parasitic tester (lpt), such as atwo pin hbm tester.

a. connectivity for each stress combination shall be verified.refer to js-001 section 5.6.2 (“non relay testers”).

b. stress may use the non-supply to non-supply stress method foundin js-001 table 2a (i.e., pin combination n+1).

c. in addition to the coupled non-supply pin pairs, adjacentnon-supply pins on the die shall be stressed in two-pin mode.

d. options outlined in js-001 section 6.6 (“hbm stressing with alow parasitic simulator”) related to lpt hbm testers may beused.